rezso/HDL

Project ID: 46761

Package: python-fpga-interchange

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Build ID Package Version Submitted Build Time Status
3891257 0.0.9-20220325.0.gitc12aff88 2 years ago 5 minutes succeeded
4094278 0.0.20-20220406.0.git3ab487ca 2 years ago 6 minutes succeeded
4306158 0.0.20-20220422.0.git1a2add79 2 years ago 5 minutes succeeded
4349995 0.0.20-20220428.0.git1d7ca360 2 years ago 5 minutes succeeded
4395453 0.0.20-20220510.0.git63291ba5 2 years ago 9 minutes succeeded
4423657 0.0.20-20220514.0.git5c059c52 2 years ago 5 minutes succeeded
4455722 0.0.20-20220527.0.git27fc1db2 2 years ago 5 minutes succeeded
4457303 0.0.20-20220527.1.git27fc1db2 2 years ago 5 minutes succeeded
4559639 0.0.20-20220527.2.git27fc1db2 2 years ago 9 minutes succeeded
4598527 0.0.20-20220705.0.git2d20fb03 2 years ago 16 minutes succeeded
4693154 0.0.20-20220705.1.git2d20fb03 1 year, 11 months ago 5 minutes succeeded
4957903 0.0.20-20221019.0.git04a02101 1 year, 9 months ago 8 minutes succeeded
5080932 0.0.20-20221019.1.git04a02101 1 year, 7 months ago 6 minutes succeeded
6154567 0.0.20-20221019.2.git04a02101 1 year, 17 days ago 9 minutes succeeded
7641892 0.0.20-20221019.3.git04a02101 a month ago 28 minutes succeeded

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