rezso/HDL

Project ID: 46761

Build 4262972

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-04-17 12:28 UTC (7 months ago)
Started:
2022-04-17 12:29 UTC (7 months ago)
Finished:
2022-04-17 12:34 UTC (7 months ago)
Build time:
5 minutes
Build timeout:
5 hours
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
pyverilog
Version:
1.3.0-20210718.0.git2a42539b
Source Type:
SRPM or .spec file upload
File Name:
pyverilog-1.3.0-20210718.0.git2a42539b.src.rpm