rezso/HDL

Project ID: 46761

Package: pyverilog

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rezso/HDL/pyverilog

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Build ID Package Version Submitted Build Time Status
4262972 1.3.0-20210718.0.git2a42539b 2 years ago 5 minutes succeeded
4559909 1.3.0-20210718.1.git2a42539b 2 years ago 6 minutes succeeded
4632608 1.3.0-20210718.2.git2a42539b 2 years ago 17 minutes succeeded
5175581 1.3.0-20210718.3.git2a42539b 1 year, 6 months ago 11 minutes succeeded
5188849 1.3.0-20221223.0.git81838bc4 1 year, 6 months ago 10 minutes succeeded
6149577 1.3.0-20221223.1.git81838bc4 1 year, 16 days ago 14 minutes succeeded

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