rezso/HDL

Project ID: 46761

Build 4417438

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-17 01:18 UTC (1 year, 11 months ago)
Started:
2022-05-17 01:33 UTC (1 year, 11 months ago)
Finished:
2022-05-17 01:53 UTC (1 year, 11 months ago)
Build time:
20 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
fpga-interchange-schema
Version:
0.0-20220516.0.giteb2841ef
Source Type:
SRPM or .spec file upload
File Name:
fpga-interchange-schema-0.0-20220516.0.giteb2841ef.src.rpm