rezso/HDL

Project ID: 46761

Build 4455722

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-28 01:16 UTC (6 months ago)
Started:
2022-05-28 01:16 UTC (6 months ago)
Finished:
2022-05-28 01:21 UTC (6 months ago)
Build time:
5 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20220527.0.git27fc1db2
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20220527.0.git27fc1db2.src.rpm