rezso/HDL

Project ID: 46761

Build 4457329

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-05-29 19:42 UTC (6 months ago)
Started:
2022-05-29 19:42 UTC (6 months ago)
Finished:
2022-05-29 19:47 UTC (6 months ago)
Build time:
4 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
fpga-interchange-schema
Version:
0.0-20220516.1.giteb2841ef
Source Type:
SRPM or .spec file upload
File Name:
fpga-interchange-schema-0.0-20220516.1.giteb2841ef.src.rpm