rezso/HDL

Project ID: 46761

Build 4559909

General Information

Status:
succeeded - Successfully built.
Submitted:
2022-06-23 21:59 UTC (1 year, 10 months ago)
Started:
2022-06-23 22:00 UTC (1 year, 10 months ago)
Finished:
2022-06-23 22:06 UTC (1 year, 10 months ago)
Build time:
6 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
pyverilog
Version:
1.3.0-20210718.1.git2a42539b
Source Type:
SRPM or .spec file upload
File Name:
pyverilog-1.3.0-20210718.1.git2a42539b.src.rpm