rezso/HDL

Project ID: 46761

Build 7641892

General Information

Status:
succeeded - Successfully built.
Submitted:
2024-06-21 08:30 UTC (23 days ago)
Started:
2024-06-21 08:33 UTC (23 days ago)
Finished:
2024-06-21 09:01 UTC (23 days ago)
Build time:
28 minutes
Build timeout:
2 days
Networking enabled:
True
Directory:
HDL
Built by:
rezso

Source

Package:
python-fpga-interchange
Version:
0.0.20-20221019.3.git04a02101
Source Type:
SRPM or .spec file upload
File Name:
python-fpga-interchange-0.0.20-20221019.3.git04a02101.fc41.src.rpm